module SampleDBoard(
	input				Clkin50M,	//50M

	//ADC IO		
	output				ADCclkA,	//50M ADC控制
	input				FclkA,		//50M
	input				DclkA,		//300M 串行跟随时钟
	input				ADCinA1,ADCinA2,ADCinA3,ADCinA4,ADCinA5,ADCinA6,ADCinA7,ADCinA8,

	output				ADCclkB,	//50M ADC控制
	input				FclkB,		//50M
	input				DclkB,		//300M 串行跟随时钟
	input				ADCinB1,ADCinB2,ADCinB3,ADCinB4,ADCinB5,ADCinB6,ADCinB7,ADCinB8,

	//ADC控制		
	output				AFE_SYNCA,
	output				AFE_RESETA,
	output				AFE_SENA,
	output				AFE_SCLKA,
	output				AFE_SDATAA,
	input				AFE_SDOUTA,

	output				AFE_SYNCB,
	output				AFE_RESETB,
	output				AFE_SENB,
	output				AFE_SCLKB,
	output				AFE_SDATAB,
	input				AFE_SDOUTB,

	input				IOclk0,IOclk1,//底板时钟

	output		[15:0]	DATA,
	input				DATA_CS,
	output				DATA_CLK,

	input				MUT_CLK,
	input				MUT_CS,
	input				MUT_MOSI,
	output				MUT_MISO,

	input				TR_IN,
	output				TR_OUT,

	input		[3:0]	SEQ,

	output				IOa,IOb,IOc,IOd,IOe,IOf,IOg,IOh,IOi,IOj//测试IO
);

//test IO
assign IOa = TR_IN;
assign IOb = TR_IN;
assign IOc = TR_IN;
assign IOd = TR_IN;
assign IOj = SEQ[0];

wire Clk;
wire clk100M;
wire clk20M;
wire clkSam;
wire clk10M;
wire clk200M;
wire plllock;
PLLCLK UCLK(
	.inclk0(IOclk0),
	.c0(Clk),
	.c1(clk100M),
	.c2(clk20M),
	.c3(clkSam),
	.c4(clk200M),
	.locked(plllock)
);

/*----------------------SystemRst----------------------*/
wire rst_n;		//先低后高，上升沿
sys_rst USysRst(
	.clk(IOclk0),
	.systemclk_locked(plllock),

	.rst_n(rst_n)
);

/*--------------------------------Command From MotherBoard--------------------------------*/
wire[15:0] R_CMD;
wire[31:0] R_DATA1;
wire[31:0] R_DATA2;
wire rec_over;
sliver_read USPIR(
	.clk_in(clk100M),
	.rst_n(rst_n),
	.SPI_SDI(MUT_MOSI),
	.CS(MUT_CS),
	.SPI_SCLK(MUT_CLK),
	.CMD(R_CMD),		//地址
	.DATA(R_DATA1),		//数据
	.rec_over(rec_over)
);


/*--------------------------------Command To MotherBoard--------------------------------*/
wire[31:0] W_DATA1;
wire[31:0] W_DATA2;
wire[15:0] W_CMD;
sliver_write USPIW(
	.clk_in(clk100M),
	.rst_n(rst_n),
	.CS(MUT_CS),
	.SPI_SCLK(MUT_CLK),
	.SPI_SDI(MUT_MOSI),

	.rdA_CH(rdA_CH),
	.rdB_CH(rdB_CH),

	.DATA1(W_DATA1),
	.DATA2(W_DATA2),
	.SPI_SDO(MUT_MISO),
	.CMD(W_CMD),
	.send_flog()
);

/*--------------------------------Decode--------------------------------*/
wire[31:0] test_port;
wire enWrA,enWrB;
wire[7:0] rdA_CH;
wire[7:0] rdB_CH;
decoder Ucode(
	.clk_in(clk100M),
	.rst_n(rst_n),
	.W_CMD(W_CMD),		//写地址
	.R_CMD(R_CMD),		//读地址
	.R_DATA1(R_DATA1),	//数据指令
	.R_DATA2(R_DATA2),
	.W_DATA1(W_DATA1),
	.W_DATA2(W_DATA2),

//
	.enWrA(enWrA),
	.WrAdcA(WrAdcA),
	.rdA_CH(),
	.divinumA(divinumA),

	.DataOutA_CH1(DataOutA_CH1),
	.DataOutA_CH2(DataOutA_CH2),
	.DataOutA_CH3(DataOutA_CH3),
	.DataOutA_CH4(DataOutA_CH4),
	.DataOutA_CH5(DataOutA_CH5),
	.DataOutA_CH6(DataOutA_CH6),
	.DataOutA_CH7(DataOutA_CH7),
	.DataOutA_CH8(DataOutA_CH8),

	.enFIFORstA(enFIFORstA),
	.LVRst_nA(LVRst_nA),

	.VerusTriggerA(VerusTriggerA),
	.TriggerRangeA(TriggerRangeA),
	.TriggerLVA(TriggerLVA),
	.TriggerModeA(TriggerModeA),
	.Trigger_CHA(Trigger_CHA),
//
	.enWrB(enWrB),
	.WrAdcB(WrAdcB),
	.rdB_CH(),
	.divinumB(divinumB),

	.DataOutB_CH1(DataOutB_CH1),
	.DataOutB_CH2(DataOutB_CH2),
	.DataOutB_CH3(DataOutB_CH3),
	.DataOutB_CH4(DataOutB_CH4),
	.DataOutB_CH5(DataOutB_CH5),
	.DataOutB_CH6(DataOutB_CH6),
	.DataOutB_CH7(DataOutB_CH7),
	.DataOutB_CH8(DataOutB_CH8),

	.enFIFORstB(enFIFORstB),
	.LVRst_nB(LVRst_nB),

	.VerusTriggerB(VerusTriggerB),
	.TriggerRangeB(TriggerRangeB),
	.TriggerLVB(TriggerLVB),
	.TriggerModeB(TriggerModeB),
	.Trigger_CHB(Trigger_CHB),

	.rd_ram(rd_ram),
	.rd_ram0(rd_ram0),

	.enTst(enTst),
	.q_out(q_out),
	.test_port(test_port)

);

/*--------------------------------AFE5801--------------------------------*/
wire[11:0] ADCdataA1,ADCdataA2,ADCdataA3,ADCdataA4,ADCdataA5,ADCdataA6,ADCdataA7,ADCdataA8;
wire[11:0] DataOutA_CH1,DataOutA_CH2,DataOutA_CH3,DataOutA_CH4,DataOutA_CH5,DataOutA_CH6,DataOutA_CH7,DataOutA_CH8;
wire[7:0] enFIFORstA;
wire LVRst_nA;
wire[13:0] divinumA;
wire VerusTriggerA;
wire[13:0] TriggerRangeA;	//预存储深度，0~100%，总计16k
wire[12:0] TriggerLVA;
wire[7:0] Trigger_CHA;
wire[1:0] TriggerModeA;
wire TriggerRange_gtA;
wire TriggerSignalA;
wire rd_rdyA,rd_rdyB;
assign TR_OUT = TriggerSignalA || TriggerSignalB;
assign DATA_CLK = TriggerRange_gtA && TriggerRange_gtB;
assign DATA[0] = rd_rdyA && rd_rdyB;
wire[14:0] rd_ram;
wire[13:0] rd_ram0;
rdfromadc UArd(
	.Clkin60M(clkSam),
	.rst_n(rst_n),
	.clk_in(clk100M),

	.rd_CH(rdA_CH),

	.enFIFORst(enFIFORstA),
	.LVRst_n(LVRst_nA),
	.divinum(divinumA),
/*--------------------------------触发所需的信号--------------------------------*/
	.Trigger_CH(Trigger_CHA),			//触发通道选中：0选空，1选中
	.TriggerMode(TriggerModeA),			//边沿触发选择：01为上升沿，10为下降沿
	.TriggerLV(TriggerLVA),			//触发电平设置
	.TriggerRange(TriggerRangeA),		//预存储深度，0~100%，总计16k
	.SamplDivinum(),		//采样率衰减倍数X：X=0为50M，X≠0为50M/X
	// .VerusTrigger(SEQ[0]),		//底板发出的触发信号，接收信号后开始将数据存入FIFO
	.VerusTrigger(TR_IN),		//底板发出的触发信号，接收信号后开始将数据存入FIFO

	.TriggerST(DATA_CS),			//底板发出的允许触发信号
	.DTriggerSignal(TriggerSignalA),		//产生的触发信号，该信号产生后关闭触发功能
	.DTriggerRange_gt(TriggerRange_gtA),		//预存储数据存满标志


	.ADCclk(ADCclkA),
	.Fclk(FclkA),
	.Dclk(DclkA),

	.ADCin1(ADCinA1),
	.ADCin2(ADCinA2),
	.ADCin3(ADCinA3),
	.ADCin4(ADCinA4),
	.ADCin5(ADCinA5),
	.ADCin6(ADCinA6),
	.ADCin7(ADCinA7),
	.ADCin8(ADCinA8),

	.DataOut_CH1(DataOutA_CH1),
	.DataOut_CH2(DataOutA_CH2),
	.DataOut_CH3(DataOutA_CH3),
	.DataOut_CH4(DataOutA_CH4),
	.DataOut_CH5(DataOutA_CH5),
	.DataOut_CH6(DataOutA_CH6),
	.DataOut_CH7(DataOutA_CH7),
	.DataOut_CH8(DataOutA_CH8)
);

wire[11:0] ADCdataB1,ADCdataB2,ADCdataB3,ADCdataB4,ADCdataB5,ADCdataB6,ADCdataB7,ADCdataB8;
wire[11:0] DataOutB_CH1,DataOutB_CH2,DataOutB_CH3,DataOutB_CH4,DataOutB_CH5,DataOutB_CH6,DataOutB_CH7,DataOutB_CH8;
wire[7:0] enFIFORstB;
wire LVRst_nB;
wire[13:0] divinumB;
wire VerusTriggerB;
wire[13:0] TriggerRangeB;	//预存储深度，0~100%，总计16k
wire[31:0] TriggerLVB;
wire[7:0] Trigger_CHB;
wire[1:0] TriggerModeB;
wire TriggerRange_gtB;
wire TriggerSignalB;
rdfromadc_b UBrd(
	.Clkin60M(clkSam),
	.rst_n(rst_n),
	.clk_in(clk100M),

	.rd_CH(rdB_CH),

	.enFIFORst(enFIFORstB),
	.LVRst_n(LVRst_nB),
	.divinum(divinumB),
/*--------------------------------触发所需的信号--------------------------------*/
	.Trigger_CH(Trigger_CHB),			//触发通道选中：0选空，1选中
	.TriggerMode(TriggerModeB),			//边沿触发选择：01为上升沿，10为下降沿
	.TriggerLV(TriggerLVB),			//触发电平设置
	.TriggerRange(TriggerRangeB),		//预存储深度，0~100%，总计16k
	.SamplDivinum(),		//采样率衰减倍数X：X=0为50M，X≠0为50M/X
	// .VerusTrigger(SEQ[0]),		//底板发出的触发信号，接收信号后开始将数据存入FIFO
	.VerusTrigger(TR_IN),		//底板发出的触发信号，接收信号后开始将数据存入FIFO

	.TriggerST(DATA_CS),			//底板发出的允许触发信号
	.DTriggerSignal(TriggerSignalB),		//产生的触发信号，该信号产生后关闭触发功能
	.DTriggerRange_gt(TriggerRange_gtB),		//预存储数据存满标志


	.ADCclk(ADCclkB),
	.Fclk(FclkB),
	.Dclk(DclkB),

	.ADCin1(ADCinB1),
	.ADCin2(ADCinB2),
	.ADCin3(ADCinB3),
	.ADCin4(ADCinB4),
	.ADCin5(ADCinB5),
	.ADCin6(ADCinB6),
	.ADCin7(ADCinB7),
	.ADCin8(ADCinB8),

	.DataOut_CH1(DataOutB_CH1),
	.DataOut_CH2(DataOutB_CH2),
	.DataOut_CH3(DataOutB_CH3),
	.DataOut_CH4(DataOutB_CH4),
	.DataOut_CH5(DataOutB_CH5),
	.DataOut_CH6(DataOutB_CH6),
	.DataOut_CH7(DataOutB_CH7),
	.DataOut_CH8(DataOutB_CH8)
);

wire[23:0] WrAdcA,WrAdcB;
wrtoadc UAwr(
	.en(enWrA),		//posedge
	.Clkin(clk20M),
	.data(WrAdcA),	//addr*8 data*16
	.SCLK(AFE_SCLKA),
	.SEN(AFE_SENA),
	.SDATA(AFE_SDATAA)
);

wrtoadc UBwr(
	.en(enWrB),		//posedge
	.Clkin(clk20M),
	.data(WrAdcB),	//addr*8 data*16
	.SCLK(AFE_SCLKB),
	.SEN(AFE_SENB),
	.SDATA(AFE_SDATAB)
);

/*--------------------------------FIFO--------------------------------*/
reg[11:0] num;
always@(posedge Clk)
begin
	if(!rst_n)
	begin
		num <= 12'h0;
	end
	else
	begin
		if(&num)
			num <= 12'h0;
		else
			num <= num + 1'b1;
	end
end

wire[23:0] q_out;
wire enTst;
// FIFO24 U2(
// 	.aclr(!rst_n),

// 	.data(num),
// 	.wrclk(Clk),
// 	.wrreq(1'b1),

// 	.rdclk(enTst),
// 	.rdreq(1'b1),

// 	.q(q_out),
// 	.rdempty(),
// 	.wrfull()
// );

endmodule
